Sense amplifier circuit for use in a semiconductor memory device

摘要

An input/output sense amplifier circuit of a semiconductor memory device is disclosed which comprises a current sense amplifier, a voltage sense amplifier and a latch circuit. The latch circuit includes a first differential amplifier for receiving the differential signals from the voltage sense amplifier; a second differential amplifier for receiving the differential signals from the voltage sense amplifier; and a gain varying circuit coupled between output terminals of the first and second differential amplifiers and setting a voltage gain of each of the first and second differential amplifiers that varies in response to the latch signal. By this configuration, a time normally required to be provided to the latch signal is obviated, thus reducing lead time of the memory device.