| 摘要 |
PROBLEM TO BE SOLVED: To reduce a main driving frequency by reducing the frequency of a first clock signal as compared with the frequency of a source video signal by the set number of a video signal. SOLUTION: The source clock SCL of the half frequency of a frequency is impressed on an m-bit shift register 21, which generates latch pulses. Moreover, data separated into odd numbers and even numbers at the outside are respectively latched into first and second latch parts 22, 23. Three kinds of latched n-bit odd number data and three kinds of latched n-bit even number data are respectively latched in 3m×n-bit first latches 25a, 26a of odd and even lines by the latch pulses of the shift register 21. Moreover, line data stored in 3m×n-bit second latches 25b, 26b of odd numbers and even numbers select voltages being in two reference voltages by D/A converters 27, 28. At this time, a line converting logic 24 changes changes over polarities of voltages. Then, selected reference voltages are impressed on liquid crystal via data output circuits 29, 30 as stabilized voltages.
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