Method of manufacturing a semiconductor device having reduced power consumption without a reduction in the source/drain breakdown voltage

摘要

An SOI layer is formed on a silicon substrate with a buried insulating layer therebetween. An SOI-MOSFET is formed including a drain region and a source region that are formed to define a channel formation region at the SOI layer and including a gate electrode layer opposite to the channel formation region with an insulating layer therebetween. A field-shield (FS) isolation structure is formed to have an FS plate opposite to a region of the SOI layer in the vicinity of the edge portion of the drain region and the source region, and to electrically isolate the SOI-MOSFET from other elements by applying a prescribed potential to the FS plate to fix the potential of the region of the SOI layer opposite to the FS plate. The channel formation region includes the edge portions on both sides and a central portion between the edge portions in a direction of a channel width, and a channel length at the edge of prescribed region is smaller than a channel length at the central portion.