| 摘要 |
A method is described for controlling a cache memory that may be either a direct-mapped or two-way set-associative cache. The described method is performed by a configurable cache controller. The cache controller receives a configuration signal having first and second states, with the configuration signal of the first state configuring the cache controller to monitor and control a direct-mapped cache, and the configuration signal of the second state configuring the cache controller to monitor and control a two-way set-associative cache. The cache controller includes first and second comparators, each able to compare respective first and second cache tags to a memory address. Both of the comparators are enabled when monitoring cache hits to a two-way set-associative cache, whereas only one of the comparators is enabled when monitoring a direct-mapped cache. The cache controller also includes first and second control circuits, each receiving a hit signal produced by a respective one of the comparators. Thus, both of these control circuits may operate when the cache controller monitors and controls a two-way set-associative cache, while only one of the control circuits will be selectively enabled when the cache controller monitors and controls a direct-mapped cache. The two-state configuration signal may be conveniently provided by a flip-flop or other programmable element whose value is set during computer system initialization routines.
|
