发明名称 Memory pool control circuit and memory pool control method
摘要 A memory pool control circuit according to the invention is provided with a CAM (content addressable memory: associative memory) 11. It further has a monitoring module 12, an area unlocking module 13, a local accessing module 14, an area locking module 15, a search control machine 16, and a timer 17. A plurality of tasks (processes) are operating on a processor 18, and one memory 19 is commonly used by the plurality of tasks (processes). When a task (process) has secured a memory space (called a block here), free areas therein are managed by a group of pointers. A block is divided into a plurality of fixed length fields. A group of flags match the memory space (block) in one-to-one correspondence. The flag group indicate whether or not individual fields are being used, i.e. the flag group indicates whether each individual field is being used or unused (free).
申请公布号 US6425048(B1) 申请公布日期 2002.07.23
申请号 US19990472038 申请日期 1999.12.27
申请人 NEC CORPORATION 发明人 KAGANOI TERUO
分类号 H01L21/8247;G06F9/50;G06F12/02;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G06F12/14 主分类号 H01L21/8247
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