Planarization method of insulating layer for semiconductor device

摘要

A method of planarizing an insulating layer for a semiconductor device, whereby a semiconductor substrate having a stepped surface due to material layer patterns of various sizes on the surface thereof is prepared. An interlayer insulating layer formed of an organic, low dielectric material covers the stepped surface of the semiconductor substrate. A capping insulating layer is formed on the interlayer insulating layer. A portion of the interlayer insulating layer which is higher than another portion of the interlayer insulating layer is selectively exposed by performing a partial chemical-mechanical polishing process on the capping insulating layer. The exposed portion of the interlayer insulating layer is plasma-processed to a predetermined depth. An entirely planarized interlayer insulating layer is formed by performing a blanket chemical-mechanical polishing process on the plasma processed portion of the interlayer insulating layer and the capping insulating layer. A silicon-methyl group bond is transformed into a silicon-hydroxide group bond by the plasma process in the organic low dielectric material.