发明名称 Parallel processor
摘要 A parallel processor system has a plurality of nodes interconnected by a network for communication under control of a network interface controller of each node. The network interface controller includes a message reception controller for receiving a message from another node and judging illustratively the status of message reception and the need to return an acknowledge message; an acknowledge generating unit for generating an acknowledge message transmission request based on predetermined information in the message and the reception status when the return of an acknowledge message is judged to be necessary; and a message transmission controller for receiving an acknowledge the message transmission request and generating and returning an acknowledge message correspondingly. At the receiving node, the network interface controller can return an acknowledge message without processor intervention.
申请公布号 US6424870(B1) 申请公布日期 2002.07.23
申请号 US19980117867 申请日期 1998.08.07
申请人 HITACHI, LTD. 发明人 MAEDA HIROMITSU;HAMILTON PATRICK
分类号 H04L1/16;H04L1/18;H04L12/56;H04L29/06;(IPC1-7):G05B19/18 主分类号 H04L1/16
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