| 摘要 |
<p>The present invention provides a multi-bits non-volatile memory circuit having a cell transistor with non-conductive trap gate which has a cell array capable of reading a plural data simultaneously. The present invention is a non-volatile memory circuit in which a plurality of cell transistors M having a non-conductive trapping gate TG are arranged, comprising: a plurality of source-drain lines SDL, which are connected commonly with the source-drain regions SD1, SD2 of cell transistors adjacent in row direction, wherein these adjacent source-drain lines are set to a floating state F, a read-out voltage application state BL, a reference voltage state 0V, a read-out voltage state BL, and a floating state F, and the source-drain lines SDL in the read-out voltage state is caused to function as bit lines, such that a plurality of data are read out simultaneously. The above states are generated by the page buffer P/B connected to the source-drain line. The data read and hold are performed by the page buffer. <IMAGE></p> |
