| 摘要 |
<p>PROBLEM TO BE SOLVED: To easily reconcile improvement of degree of integration and lowering of an operating voltage of a memory cell. SOLUTION: A semiconductor substrate has impurity diffusion layers for source and drain electrodes and first floating gate electrodes 42 formed on channel region defined by the impurity diffusion layers with gate insulating films in between. On the impurity diffusion layers, in addition, second floating gate electrodes 47 with tunnel insulating films which are thinner than the gate insulating films in between, and third floating gate electrodes 51 which are in contact with the first and second floating gate electrodes 42 and 47, are formed and, on the third floating gate electrodes 51, a control gate electrode 53 is formed with an insulating film 52 in between.</p> |
