发明名称 Array board interconnect system and method
摘要 The FPGA array in the Simulation system is provided on the motherboard through a particular board interconnect structure to provide easy expandability and maximize packaging density with a single PCB design. Each chip may have up to eight sets of interconnections, where the interconnections are arranged according to adjacent direct-neighbor interconnects (i.e., N[73:0], S[73:0], W[73:0], E[73:0]), and one-hope neighbor interconnects (i.e., NH[27:0], SH[27:0], XH[36:0], XH[72:37]), excluding the local bus connections, within a single board and across different boards. Each chip is capable of being interconnected directly to adjacent neighbor chips, or in one hop to a non-adjacent chip located above, below, left, and right. In the X direction (east-west), the array is connected in a torus. In the Y direction (north-south), the array is connected in a column. The interconnects alone can couple logic devices and other components within a single board. However, the inter-board connectors are provided to couple these boards and interconnects together across different boards to carry signals between (1) the PCI bus via the motherboard and the array boards, and (2) any two array boards, all without passing through a backplane or motherboard to achieve the highest packaging density. A motherboard connector connects the board to the motherboard, and hence, to the PCI bus, power, and ground. For some boards, the motherboard connector is not used for direct connection to the motherboard. In a six-board configuration, only boards 1, 3 and 5 are directly connected to the motherboard while the remaining boards 2, 4, and 6 rely on their neighbor boards for motherboard connectivity. Thus, every other board is directly connected to the motherboard, and interconnects and local buses of these boards are coupled together via inter-board connectors arranged solder-side to component-side. PCI signals are routed through one of the boards (typically the first board) only. Power and ground are applied to the other motherboard connectors for those boards. Placed solder-side to component-side, the various inter-board connectors allow communication among the PCI bus components, the FPGA logic devices, memory devices, and various Simulation system control circuits.
申请公布号 US6421251(B1) 申请公布日期 2002.07.16
申请号 US19980019383 申请日期 1998.02.05
申请人 LIN SHARON SHEAU-PYNG 发明人 LIN SHARON SHEAU-PYNG
分类号 G06F17/50;(IPC1-7):H05K7/10;H05K7/06;H05K1/14 主分类号 G06F17/50
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