AMPLIFIER WITH REDUCED INPUT CAPACITANCE

摘要

A JFET preamplifier for use with a high impedance transducer, having an inherently capacitive input bias impedance. The capacitance of the input bia s impedance is effectively neutralized by capacitively coupling the JFET gate bias circu it to the source electrode of the JFET. The JFET preamplifier is configured as a sourc e follower which reduces any capacitance between the JFET gate and source electrode by the open loop gain of the amplifier. By capacitively coupling the JFET gate bias circuit capacitance to the JFET source electrode, the overall input capacitance of t he preamplifier stage is reduced.