发明名称 |
Method and system for a speedup of a bit multiplier |
摘要 |
A method and system is provided which overlaps the process of partial product reduction and the final adder in both higher- and lower-order bits when performing multiplication. The method and system reduces the number of left-over bits such that the final addition on these bits requires fewer logic stages to complete its process thereby reducing the propagation delay.
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申请公布号 |
US6421699(B1) |
申请公布日期 |
2002.07.16 |
申请号 |
US19990272489 |
申请日期 |
1999.03.19 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DHONG SANG HOO;LIN PERNG SHYONG;SILBERMAN JOEL ABRAHAM |
分类号 |
G06F7/50;G06F7/52;G06F7/533;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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