发明名称 |
Efficient top-down characterization method |
摘要 |
A method of efficiently characterizing modules of an integrated circuit (IC) design using a logic synthesis tool comprising the steps of defining a list of instances of the modules to characterize, and characterizing entire modules of said list of instances of the modules using a single invocation of characterize command of the logic synthesis tool.
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申请公布号 |
US6421818(B1) |
申请公布日期 |
2002.07.16 |
申请号 |
US19980027438 |
申请日期 |
1998.02.20 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
DUPENLOUP GUY;CLEEREMAN KEVIN CHRISTOPHER |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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