| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronous output circuit that prevents access from being increased by enabling the output of a logic circuit section after a prescribed time from the state transition of an input signal. SOLUTION: When a signal (a) transits to an 'H' level at time t1, an output of an input signal transition detection circuit 1 goes to the 'H' level at time t2 and an output ENA1 of an input enable signal generating circuit 5 goes to the 'H' level. When the ENA1 reaches the 'H' level, a 2-bit counter is reset to have an output of '00'. When the signal (b) transits to the 'H' level at time t3, since the ENA1 is at the 'H' level in this state, the signals a, b propagate to a logic circuit section 6 at time t4 and the input enable signal ENA1 goes to an 'L' level at a succeeding rise of the clock CLK, that is, at time t5. Since the 2-bit counter stops its operation at time t6 and an output enable signal ENA2 goes to an 'L' level, an output driver section 8 outputs the 'H' level synchronously with rise of the clock CLK.
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