| 摘要 |
PURPOSE: An apparatus and a method for improving fault coverage in a partial scan chain are provided to reduce the time for a test on a mechanism for running a test mode controlled by a scan chain block and to minimize the area of a chip by excluding a sequential logic element for a separate scan chain. CONSTITUTION: The system includes a scan chain block(230), a non-scan chain block(280), and plural multiplexers(350). In the scan chain block, plural sequential logic elements are serially connected between partial scan mode input/output pins, and are synchronized to a clock under the logic of a scan enable signal. The scan chain block sequentially outputs data to the output terminals of respective sequential logic elements. The non-scan chain block consists of plural sequential logic elements and plural combinational logic elements. The multiplexers are connected between respective output terminals of the sequential logic elements in the scan chain block and respective input terminals of the combinational logic elements. In a test mode, if a scan enable signal is logic high, the data generated in respective output terminals of the sequential logic elements are applied to respective input terminals of the combinational logic elements.
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