| 摘要 |
PROBLEM TO BE SOLVED: To generate a reference level without using a dummy cell in a ferroelectric memory device having 1T1C memory cell structure. SOLUTION: A PMOS(P-channel metal oxide semiconductor) transistor 30 is connected additionally between a node SAP1 being a control terminal of a sense amplifier 20A and a node SAP2, thereby offset is caused in the sense amplifier 20A. A sense amplifier control signal SAP is connected directly to the node SAP2, and the sense amplifier control signal SAP is connected to the node SAP1 through the PMOS transistor 30. Also, the offset level of the sense amplifier 20A is set by adjustment of a potential of an offset control signal OFS being a gate input of the PMOS transistor 30. Since a reference level can be generated without using a dummy cell, a ferroelectric memory characteristic of high speed and high reliability is implemented.
|
