Stacked-fringe integrated circuit capacitors

摘要

A capacitorÄ10, 50, 100Ü that is adapted for construction over a substrateÄ11Ü in the metal interconnect layers provided by conventional integrated circuit processes. The capacitorÄ10, 50, 100Ü includes a first conducting layerÄ14, 102Ü separated from the substrateÄ11Ü by a first dielectric layerÄ20Ü and a second conducting layerÄ15, 102Ü separated from the first conduction layer by a second dielectric layerÄ19Ü. The second conducting layerÄ15, 102Ü is divided into a plurality of electrically isolated conductors in an ordered array. Every other one of the conductors is connected to a first terminalÄ31Ü, and the remaining conductors are connected to a second terminalÄ32Ü. The first conducting layerÄ14, 102Ü includes at least one conductor which is connected to the first terminalÄ31Ü. In one embodiment of the invention, the first conducting layerÄ14, 102Ü also includes a plurality of electrically isolated conductors in an ordered array, every other one of the conductors being connected to the first terminalÄ31Ü and the remaining conductors being connected the second terminalÄ32Ü.