| 摘要 |
PURPOSE: A row part circuit of an SDRAM is provided, which increases a stability of a circuit by synchronizing a signal flow of a row path to an external clock and reducing a delay factor. CONSTITUTION: According to the row part circuit of an SDRAM comprising a sense amplifier(100) and a memory cell(200) connected by a bit line and a bit line bar each other, a command buffer(11) outputs an internal command signal by receiving an external command signal. A command decoder(12) outputs an active signal and a precharge signal in response to an internal clock by receiving an internal command signal of the command buffer. A sense amplifier timing control part(13) outputs a sense amplifier timing control signal in response to an active signal of the command decoder. A sense amplifier enable part(14) outputs a read enable signal and a sense amplifier enable signal by receiving an output signal of the sense amplifier timing control part and a precharge signal of the command decoder part. An address buffer(15) outputs an internal address signal by receiving the internal address signal. An address latch(16) outputs the internal address signal in response to an internal clock. An X-decoder(17) selects a desired main word line by receiving an output of the address latch. And a main word line driving part(18) drives a word line of the memory cell by receiving a main word line signal selected in the X-decoder.
|
