| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a level shifter which can be operated sufficiently even if operation voltage is dropped and a semiconductor memory provided with the level shifter in which high integration can be performed further. SOLUTION: This device has a latch circuit having a node ND1 of which voltage is VH or VL and a node 2 of which voltage is VL or VH, a capacitor C1 of which one end is connected to the node N1, and a capacitor C2 of which one end is connected to the node ND2. Voltage Vh is inputted to the other end of the capacitor C1, and voltage V1 being an inverse signal of the voltage Vh is inputted to the other end of the capacitor C2.</p> |
