| 摘要 |
PURPOSE: A method for efficiently designing a chip through grouping by using a standard cell is provided to reduce the time for designing a chip, to efficiently use chip area, and to solve the timing problem during chip designing by an adopting grouping with a standard cell. CONSTITUTION: A circuit to design is divided into various function blocks. The function blocks are expressed by a program. The data in the register transfer level are converted into the data in the gate level through the synthesis of definite logic gates. The data expressed in the gate level are simulated logically. The data are grouped depending on the approximation of the functions or the necessity of timing margin. The grouped data are moduled. The grouped modules are automatically arrange-routed. Logic and timing simulation is performed with the data files. Automatic arrange-routing is performed with the rest of the data.
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