| 摘要 |
PROBLEM TO BE SOLVED: To provide a sample-and-hold circuit in which offset quality is restricted to a constant value. SOLUTION: Voltage B that is made to differ by a constant value from voltage A indicated by an analog input voltage signal IN is generated by a constant difference voltage generating circuit 13, offset quantity generated by influence of clock field through is restricted to a constant value by selecting and outputting the voltage B from a multiplexer 14 by a switching clock CLK and applying it to a gate of a NMOS transistor 11 and performing sample-and- hold for an analog input voltage signal IN to a capacitor 12, even when magnitude of the analog input voltage signal IN is varied.
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