| 摘要 |
PROBLEM TO BE SOLVED: To provide a cache coincidence controller capable of reducing requested quantity of cache coincidence control even for a program with low re-accessibility to the same block. SOLUTION: CPU node control circuits 120 are provided to the respective nodes of a multi-CPU system constituted by connecting plural CPU nodes (100a to 100b), plural memory nodes (200a to 200b) and plural I/O nodes (300a to 300b) by a network 400, access right memories 151 to manage access rights of the nodes by a unit (enlarged block) larger than block size of an internal cache of a CPU are provided in the respective CPU node control circuits, the access right memories 151 are referred to for memory access, when the present node owns the access right of the enlarged block including an accessing object block, the cache coincidence control of other nodes is omitted and the block is accessed.
|
