| 摘要 |
PROBLEM TO BE SOLVED: To reduce TAT for verifying the layout by eliminating the redundant error graphic and eliminating the error graphic. SOLUTION: This design checking method has a flow A2 as a flow of the total processing of a layout verifying tool, a DRC flow B2 composing the flow A2 as the total processing of the DRC processing, and including an additional information adding step B27 and an error graphic compressing step C1, an error graphic outputting flow D1 composing the flow A2 as the total processing for outputting the error graphic, and an error compression flow C1 as the error compressing processing for compressing the error graphic to be outputted, by eliminating the redundant error graphic.
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