DRAM cell arrangement used for a semiconductor storage device comprises a matrix arrangement of storage cells stacked over each other as layers, and a capacitor connected to the MOS transistor

摘要

The channel regions, which are arranged along one of the columns of the storage cell matrix, are parts of a connecting element surrounded by a gate dielectric layer. The gate electrodes of the MOS transistors of a row are parts of a strip-shaped word line. According to the invention, a vertical double gate MOS transistor having gate electrodes, which are formed in the trenches on both sides of the assigned connecting element, of the assigned word line, is provided at each point of intersection of the storage cell matrix.