NOR-TYPE FLASH MEMORY DEVICE AND FABRICATING METHOD THEREOF

摘要

PURPOSE: A NOR-type flash memory device is provided to increase a cell density and integration of memory cells, by changing the structure of a split gate memory cell so that the number of bit line contacts is remarkably decreased. CONSTITUTION: N+ source regions(204a,204a') are formed in the surface of a P-type semiconductor substrate(200), separated from each other by a predetermined interval. An N+ drain region(204b) is formed in the surface of the P-type semiconductor substrate between the source regions, having a junction depth shallower than the source region. The first buried N-type(BN) oxide layer(206a) is formed on the substrate in the source region. The second BN oxide layer(206b) is formed on the substrate in the drain region. Floating gates(210a) are formed in a predetermined portion of the substrate including both edges of the first BN oxide layer wherein the center of the first BN oxide layer is exposed, disposed at both sides of a coupling oxide layer(208). An isolation layer(214) is formed on the floating gate. A tunneling oxide layer(216) is formed along the exposed surface of the floating gate. A plurality of wordlines(218) are formed on the resultant structure, overlapping the floating gates and vertically crossing the first and second BN oxide layers. One bit line contact connected to the drain region exists in every three wordlines or more.