| 摘要 |
PURPOSE: An SRAM compatible memory for hiding a refresh operation using a DRAM cache memory is provided to use a DRAM cell as a data storage medium and hide a refresh operation. CONSTITUTION: An SRAM compatible memory includes 64 memory banks:0-63 and 64 bank access circuits(100-163). Each bank access circuits(100-163) receives outer addresses(AD(0:16)), a read command signal(RD), and a write command signal(WD). Each memory bank: 0-63 includes DRAM memory cells arranged on 16K rows and 32 columns. Each memory bank: 0-63 is coupled to an input/output bus mediation portion(171). Input/output data(DIN/DQ) are transmitted from the memory banks: 0-63 through the input/output bus mediation portion(171). The DRAM memory cells perform refresh operations within a predetermined refresh period in order to store data. In addition, the SRAM compatible memory includes a DRAM cache memory(173), a cache access circuit(175), an access selection circuit(177), a flag memory(179), a tag memory(181), a comparator(183), and a bank mediator(185).
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