发明名称 TRANSMITTER, RECEIVER, AND COMMUNICATION METHOD
摘要 <p>A separator circuit (250) extracts a systematic bit and a parity bit from a received packet and separates them. A combining circuit (204) symbol-combines the separated systematic bit in a unit of the current resending with the systematic bits acquired in the units of the past resendings. A decoder circuit (214) likelihood-combines the separated parity bit with the parity bits acquired in the units of the past resendings and error-correction-decodes the symbol-combined systematic bits by using the likelihood-combined parity bits as check bits. Thus, the reception level and the ability of correction of errors can be enhanced, and the number of resendings until no error is detected, thereby improving the throughput.</p>
申请公布号 WO2002054659(P1) 申请公布日期 2002.07.11
申请号 JP2001011448 申请日期 2001.12.26
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