发明名称 MULTILAYER INTERCONNECTION STRUCTURE OF SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
摘要 PURPOSE: A multilayer interconnection structure of a semiconductor device is provided to relax thermal stress concentrating on a via contact in an alloy process and improve the reliability of contact interconnection by introducing a P-poly pattern in a multilayer interconnection formation. CONSTITUTION: A P-poly pattern(102) is formed on the insulation substrate(100). The first interlayer dielectric(104) comprising the first via hole(h1) is formed on the resultant structure in order to expose partially the surface of the P-poly pattern. The first/second metal interconnections(106,108) comprising a through hole(t) are formed on the first interlayer dielectric to connect the first via hole(h1,h2). A conductive plug(110) is formed to meet the P-poly pattern. A passivation layer(112) having HDP oxide/nitride stack structure is formed on the second insulation layer(108) including the conductive plug(110).
申请公布号 KR20020057340(A) 申请公布日期 2002.07.11
申请号 KR20010000328 申请日期 2001.01.04
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM, HYEON CHEOL
分类号 H01L21/3205;(IPC1-7):H01L21/320 主分类号 H01L21/3205
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