发明名称 |
Digital clock recovery system |
摘要 |
A digital clock recovery circuit. The digital clock recovery circuit uses a lumped delay line and a digital phase detector to form a recovered clock signal. The recovered clock signal is limited to one clock period of the delay line so as to prevent false locking.
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申请公布号 |
US2002090045(A1) |
申请公布日期 |
2002.07.11 |
申请号 |
US20020037671 |
申请日期 |
2002.01.03 |
申请人 |
HENDRICKSON NORM |
发明人 |
HENDRICKSON NORM |
分类号 |
H03L7/081;H03L7/087;H04J3/04;H04J3/06;H04L7/033;H04L7/04;H04L12/56;(IPC1-7):H03D3/24 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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