MEMORY ARCHITECTURE WITH CONTROLLABLE BITLINE LENGTHS

摘要

A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.