| 摘要 |
In customary EPROM processes, where the control gate is formed by a conductive poly layer on top of the floating gate, two poly layers are provided. An EPROM cell in accordance with the invention comprises a control gate formed by a well (10) of the second conductivity type, provided in a surface region (2) of a first conductivity type. The floating gate (9) extends above the well and is operated from said well by a thin gate oxide (11). The well (10) is provided with a contact region (14) of the second conductivity type, which is self-aligned with respect to the floating gate. As a result, the EPROM process only requires a single poly layer. Due to the fact that the well forming the control gate can be provided before the deposition of the poly layer, the EPROM process is compatible with standard CMOS processes. In addition, since the well is free of regions of the first conductivity type, the device is free of latch-up.
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