| 摘要 |
<p>A capacitor includes multiple tiers (302, 304, 306, 1210, 1212, 1310, 1312, 1380, Figures 3, 12, 13) which provide capacitance to a load at different inductance values. Each tier includes multiple layers (311-325, 1220, 1222, 1320, 1322, 1382, Figures 3, 12, 13) of patterned conductive material, which are separated by layers of dielectric material. In one embodiment, tiers are stacked in a vertical direction, and are electrically connected through vias (330, 332, 334, 1230, 1232, Figures 3, 12) that extend through some or all of the tiers. In another embodiment, one or more tieres (1310, 1312, Figure 13) are located in a peripheral region (1408, Figure 14) of the capacitor, and one or more other tiers (1380, Figure 13) are located in a peripheral region (1408, Figure 14) of the capacitor. In that embodiment, the center tiers and peripheral tiers are electrically connected through one or more additional layers (1370, Figure 13) of patterned conductive material. The capacitors of the various embodiments can be used as discretedevices, which are mountable on or embeddable within a housing (e.g., a package, interposer, socket or PC board), or they can be integrally fabricatad within the housing.</p> |
