| 摘要 |
PURPOSE: A flash memory device is provided to reduce the amount of cell current and improve a program speed by controlling voltage of a flash memory cell. CONSTITUTION: A flash memory device is formed with an NOR type flash memory cell array(100), a multiplexer(200), and a decoder portion(300). In the decoder portion(300), the first PMOS transistor(P21) receives the first global word line signal(GWL0). The first PMOS transistor(P21) is used as a diode. The first NMOS transistor(N21) is connected between the first node(Q21) and a ground terminal(Vss). The first NMOS transistor(N21) is driven by the first control signal(NGW0). The first inverter(I21) is connected between the first control signal input terminal and the second node(Q22). The first transfer gate(T21) is driven by a sector program signal(SPGM) and an inversion signal(SPGMb). The first transfer gate(T21) supplies electric potential of the second node(Q22) to the first source line(SOURCE0). The second PMOS transistor(P22) is connected between the second local word line signal input terminal and the first word line. The second PMOS transistor(P22) is driven by electric potential of the first node(Q21). The third NMOS transistor(N23) is connected between the second word line(WL1) and the second power terminal(VEEX). The third NMOS transistor(N23) is driven by electric potential of the second node(Q22). The fourth NMOS transistor(N24) is connected between the second word line(WL1) and the second power terminal(VEEX). The fourth NMOS transistor(N24) is driven by the second pre-decoder bar signal(XPRE1b).
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