| 摘要 |
PURPOSE: A pipe latch circuit is provided to prevent a malfunction due to an input of the second data before transition of the first control signal by controlling a switching portion. CONSTITUTION: The first and the second PMOS transistors(P31,P32) are connected between a power terminal(Vcc) and the third node(Q33). The first and the second NMOS transistors(N31,N32) are connected between the third node(Q33) and a ground terminal(Vss). The third and the fourth PMOS transistors(P33,P34) are connected between the power terminal(Vcc) and the fourth node(Q34). The third and the fourth NMOS transistors(N33,N34) are connected between the fourth node(Q34) and the ground terminal(Vss). The first latch portion(33) latches electric potential of the first node(Q31). The second latch portion(35) latches electric potential of the second node(Q32). The second NAND gate performs a logical operation for the electric potential of the first node(Q31) and an output signal of the second latch portion(35). The third NAND gate(34) performs the logical operation for the electric potential of the second node(Q32) and an output signal of the first latch portion(33). The fourth NAND gate(36) performs the logical operation for an output signal of the first latch portion(33) and the output signal of the second latch portion(35). The fifth and the sixth PMOS transistors(P35,P36) between the power terminal(Vcc) and the first output terminal(OUT1). The fifth and the sixth NMOS transistors(N35,N36) between the first output terminal(OUT1) and the ground terminal(Vss). The seventh and the eighth PMOS transistors(P35,P36) between the power terminal(Vcc) and the second output terminal(OUT2). The seventh and the eighth NMOS transistors(N37,N38) between the second output terminal(OUT2) and the ground terminal(Vss).
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