| 摘要 |
<p>PROBLEM TO BE SOLVED: To solve such a problem, especially, reduction of size of cell and process specifications that high voltage used for charging and discharging a floating gate is restricted when important design of a flash memory device is implemented. SOLUTION: In this method, a conduction state of a cell to be programmed is attained with negative word line voltage during page program operation of an array, otherwise a non-conduction state of the cell is established. Negative drain, source, and substrate voltage are applied during erasing operation, and a data pattern in a flash EPROM integrated circuit is programmed so that positive voltage to be applied to solve a disturbance problem during operation can be reduced.</p> |
