A METHOD FOR PRECISE TRAP HANDLING IN CASE OF SPECULATIVE AND OUT-OF-ORDER LOADS

摘要

A processor performs precise trap handling for out-of-order and speculative load instructions. It keeps track of the age of load instructions in a shared scheme that includes a load buffer and a load annex. All precise exceptions are detected in a T phase of a load pipeline. Data and control information concerning load operations that hit in the cache are staged in a load annex during the A1, A2, A3, and T pipeline stages until all exceptions in the same, or earlier, instruction packet are detected. Data and control information from all other load instructions is staged in the load annex after the load data is retrieved. If an exception occurs, any load in the same instruction packet as the instruction causing the exception is canceled. Any load instructions that are "younger" than the instruction that caused the exception are also canceled. The age of load instructions is determined by tracking the pipe stages of the instruction. When a trap occurs, any load instruction with a non-zero age indicator is canceled.