发明名称 |
Semiconductor memory device suitable for merging with logic |
摘要 |
Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.
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申请公布号 |
US6418067(B1) |
申请公布日期 |
2002.07.09 |
申请号 |
US20000592454 |
申请日期 |
2000.06.09 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
WATANABE NAOYA;YAMAZAKI AKIRA;ARIMOTO KAZUTAMI;FUJINO TAKESHI;HAYASHI ISAMU;NODA HIDEYUKI |
分类号 |
G11C11/409;G11C11/401;G11C11/407;G11C11/4076;G11C29/00;G11C29/04;H01L21/8242;H01L27/108;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/409 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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