| 摘要 |
A system for silicon chip evaluation comprising a chip embedded in a wafer and one or more testbench circuits embedded in the wafer, wherein the one or more testbenches provide verification of the chip. One aspect of the present invention concerns a method for silicon chip verification comprising the steps of (A) embedding a chip in a silicon wafer, (B) embedding one or more testbench circuits in the silicon wafer, and (C) communicating between the one or more testbenches and the chip to provide silicon verification of the chip.
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