| 摘要 |
A frequency synthesizer including a divide by R frequency divider providing a first input of a phase detector, a divide by N frequency divider providing a second input of the phase detector, and a voltage control oscillator (VCO) receiving the output of the phase detector and providing an input to the divide by N frequency divider, the VCO output signal being transitioned by varying the frequency division number R. The frequency division number N may also be varied to transition the VCO output signal frequency. A reference oscillator provides an input to the variable R frequency divider and may have its frequency varied to limit resolution error. For greater resolution, multiple frequency synthesizers with divide by R and N frequency dividers having variable frequency division numbers may be connected using mixers to provide a "ratio sum" synthesizer having an output frequency proportional to a sum of N/R ratios.
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