发明名称 Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment
摘要 In one embodiment, the invention is a method of forming a bus. A first conductor having a first impedance is provided, the first conductor is routed through a fifth chip. Coupling of the first conductor to a first chip with a first termination impedance occurs. Coupling of the first conductor to a second chip with a second termination impedance occurs. Coupling of the first conductor to a third chip with a third termination impedance occurs, and coupling of the first conductor to a fourth chip with a fourth termination impedance occurs.
申请公布号 US6417688(B1) 申请公布日期 2002.07.09
申请号 US19990476585 申请日期 1999.12.31
申请人 INTEL CORPORATION 发明人 DABRAL SANJAY;ZENG MING
分类号 H05K1/00;H05K1/02;H05K1/18;(IPC1-7):H03K17/16;H03K19/003 主分类号 H05K1/00
代理机构 代理人
主权项
地址