Method and apparatus for calibrating an IEEE-1394 cycle master

摘要

A cycle master in a digital network having a bus architecture that complies with the IEEE-1394 Standard for a High Performance Serial Bus is calibrated by first computing a clock offset representing a difference between a first time synchronized to each of a plurality of packet arrival events and a second time synchronized to periodic ones of said plurality of packet arrival events; and then adjusting a frame rate of said packet arrival events to compensate for said clock offset.