发明名称 ASYNCHRONOUS CLOCK SIGNAL MULTIPLEXING APPARATUS
摘要 PURPOSE: An asynchronous clock signal multiplexing apparatus having a safe mode is provided to maintain a clock operation of a clock until a stopped clock is worked again when a converting signal is generated. CONSTITUTION: The asynchronous clock signal multiplexing apparatus includes the first asynchronous/synchronous clock generator(51) which is synchronized with the second clock. The first safe flag generator(52) is synchronized with the second clock in order to generate the first safe flag signal of a low level when the second protect signal is low. The second asynchronous/synchronous clock generator(53) is synchronized with the first clock and generates the second safe flag signal of the low level when the first protect signal is low. The first clock signal generator(54) is synchronized with the first clock and generates the same signal as the first clock. The second clock signal generator(55) is synchronized with the second clock and generates the same signal as the second clock. A multiplexer(56) outputs either an output signal of the first clock generator(54) or an output signal of the second clock generator(55).
申请公布号 KR20020055297(A) 申请公布日期 2002.07.08
申请号 KR20000084720 申请日期 2000.12.28
申请人 LG ELECTRONICS INC. 发明人 CHOI, JIN HO
分类号 H04L7/02;(IPC1-7):H04L7/02 主分类号 H04L7/02
代理机构 代理人
主权项
地址