| 摘要 |
PURPOSE: An RAS(Row Address Strobe) signal input buffer circuit is provided to output a stable internal RAS signal regardless of power noise by improving a structure of an input buffer. CONSTITUTION: The first input inverter(I4) has an input terminal for receiving a power-up signal and an RAS bar signal from the outside. The first input inverter(I4) is used for inverting the received power-up signal. The first PMOS transistor(Q5) is controlled by an output of the first inverter(I4). The second PMOS transistor(Q6) and the first NMOS transistor(Q7) are controlled by the RAS bar signal. The second PMOS transistor(Q6) and the first NMOS transistor(Q7) are connected directly with the first PMOS transistor(Q5). The second NMOS transistor(Q8) is controlled by an output of the first input inverter(I4). The second inverter(I5) inverts outputs of the second PMOS transistor(Q6) and the first NMOS transistor(Q7). The third inverter(I12) inverts an internal RAS signal. The fourth, the fifth, and the sixth inverters(I11,I10,I9) delay and invert an output of the third inverter(I12). A NOR gate performs a logical operation for an output of the third inverter(I12), an output of the sixth inverter(I9), and the first inverter(I4). A switching portion is formed with a transmission gate and the seventh inverter(I6). A latch portion is formed with the eighth inverter(I7) and the ninth inverter(I8).
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