| 摘要 |
PURPOSE: A PLC circuit with reduced setting time is provided, which reduces a maximum convergence time into a half, by only adding two constant current sources to the conventional PLC circuit. CONSTITUTION: The PLL circuit of the present invention is composed of a phase comparator(100) with current mode output, constant current sources(101,200,201), a mixer(105), a LPF(103), a VCO(104) and a SW(102). The output current of the constant current sources(101,200) have the same value (I1 = I2). Moreover, an output current I3 of the constant current source(201) has a value larger than the constant current sources(101,200), for example, 50 times as much as them. In the following description, it is assumed that the VCO(104) has a positive sensitivity. A control signal LOGIC1 is given to the SW(102). In the case where the LOGIC1 is zero "0", the SW(102) becomes an open state; on the other hand, in the case where the LOGIC1 is "1", the SW(102) is short-circuited to ground. Moreover, control signals LOGIC2, LOGIC3 and LOGIC4 are given to the constant current sources(101,200,201), respectively. In the case where the LOGIC2, LOGIC3 and LOGIC4 are zero "0", each constant current source, to which the LOGIC is inputted, becomes an off state, and in the case where these LOGIC are "1", each of them becomes an on state.
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