| 摘要 |
PURPOSE: A DQ comparator for built in self test of an SDRAM is provided to check an operating state of a particular cell of the SRAM and verify a setup time and a hold time of a DQ signal by comparing a reading value of the DQ signal with an expected value of the DQ signal. CONSTITUTION: A signal detection portion(10) compares a reading value(DQ) of a DQ signal with an expected value(EDQ) of the DQ signal. A timing detection portion(20) compares a setup time with a hold time by comparing the reading value(DQ) of the DQ signal with the expected value(EDQ) of the DQ signal. The signal detection portion(10) is formed with the first register(1) for latching the reading value(DQ) and outputting a latched signal and the first exclusive OR gate(XOR1). The timing detection portion(20) is formed with a setup time delay portion(2), the second register(4), a hold time delay portion(3), the third register(5), the second exclusive OR gate(XOR2), and the third exclusive OR gate.
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