| 摘要 |
PURPOSE: A column address decoder is provided to prevent a phenomenon of time delay by using a separative structure of a write path and a read path. CONSTITUTION: A column address decoder(1) outputs signals(Y1_NEW,Y1B_NEW) to a column selector(2) according to signals(EN,FBN,EBN,YWEB) provided from a column address multiplexer(MUX). The column selector(2) selects one of a bit line of a memory cell array(3) and a write and a read bit line of a write and read circuit(4) according to the signals(Y1_NEW,Y1B_NEW) output from the column address decoder(1). A P type MOS transistor(P11) and an N type MOS transistor(N11) are connected with an enable signal input terminal and a ground of the column decoder(1). A transistor(N12) is connected with a contact point between the P type MOS transistor(P11) and the N type MOS transistor(N11). A transistor(N12) is connected a node(K11) and the ground. A P type MOS transistor(P12) and an N type MOS transistor(N13) are connected with between a supply voltage(Vcc) and a signal input terminal. The node(K11) is connected with each gate of the P type MOS transistor(P12) and the N type MOS transistor(N13). A P type MOS transistor(P12) is connected with a contact point between the P type MOS transistor(P12) and the N type MOS transistor(N13).
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