| 摘要 |
PURPOSE: An encoder for communication system composition is provided to realize a high speed data processing by processing an input bit array by byte or word to generate an output bit array. CONSTITUTION: A first shift register(11) shifts an input bit array(X0). A second shift register(12) shifts a one-shifted bit array(X1) again. A third shift register(13) shifts a two-shifted bit array(X2) again. A fourth shift register(14) shifts a three-shifted bit array(X3) again to output a four-shifted bit array(X4). A first XOR gate(15) generates a bit array(G0) from the input bit array(X0), the three-shifted bit array(X3), and the four-shifted bit array(X4). A second XOR gate(16) generates a bit array(G1) from the input bit array(X0), the one-shifted bit array(X1), the three-shifted bit array(X3), and the four-shifted bit array(X4). A MUX(multiplexor)(17) mixes the bit array(G0) generated in the first XOR gate(15) with the bit array(G1) generated in the second XOR gate(16) to generate an output bit array(G0G1).
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