发明名称 CHIP SCALE PACKAGE AND METHOD FOR FABRICATING THE SAME IN WAFER LEVEL
摘要 PURPOSE: A chip scale package and a method for fabricating the same in a wafer level are provided to emit easily generated heat and enhance productivity by using a wire bonding method. CONSTITUTION: A center pad(1a) type chip(1) is adhered to one side of a heat-sink(10). An LOC(Lead On Chip) tape(6) is adhered to both sides of the center pad(1a) formed on an upper face of the chip(1). A lead(5) of a down-set structure is adhered on the LOC tape(6). The center pad(1a) of the chip(1) is connected electrically with the lead(5) by a wire. Each upper face of the lead(5), the wire, and the chip(1) except for a front end portion of the lead(5) are sealed by a mold body. A solder ball(8) is formed on the front end portion of the lead(5). A non-conductive thermal adhesive tape(11) is adhered between the heat-sink(10) and a rear side of a chip(1).
申请公布号 KR20020053934(A) 申请公布日期 2002.07.06
申请号 KR20000081912 申请日期 2000.12.26
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHOI, HYEON YEONG
分类号 H01L23/492;(IPC1-7):H01L23/492 主分类号 H01L23/492
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