发明名称 HIGH-SPEED DEBLOCKING FILTER DEVICE
摘要 PURPOSE: A high-speed deblocking filter device is provided to input data by even times of 8-bit and divide the inputted data by 8 bits, and to perform parallel processing for filtering simultaneously by a plurality of filter processors, then to pack the processed 8-bit data to be outputted by even times of 8-bit. CONSTITUTION: A controller(20) receives a control signal to control operations of each unit in a deblocking filter device. A data input unit(10) receives pixel data according to the signal of the controller. An addressing unit(30) outputs an appropriate memory address and a memory control address according to the signal of the controller. A plurality of filter processors(40-1,40-2) perform deblocking filtering for the data received from the data input unit. A data output unit(50) receives the processed data from the filter processors. And the data are inputted and outputted by even times of 8-bit, and deblocking filtering is processed in parallel simultaneously by the filter processors.
申请公布号 KR20020053336(A) 申请公布日期 2002.07.05
申请号 KR20000082892 申请日期 2000.12.27
申请人 CURITEL COMMUNICATIONS, INC. 发明人 RYU, MYEONG BUN
分类号 H04N7/24;(IPC1-7):H04N7/24 主分类号 H04N7/24
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