LOW VOLTAGE SAMPLE AND HOLD CIRCUIT WITH VOLTAGE RANGE COMPRESSION AND EXPANSION

摘要

An electronic circuit comprising a sample and hold circuit (S/H) for sampling and temporarily holding an input data signal (Ui, Ii), comprising means (S; TS) for the sampling of a data voltage (U1) which corresponds to the input data signal (Ui, Ii), a capacitive element (C1) for temporarily holding the sampled voltage (UC), and means (CPR) for compressing the voltage range of the data voltage (U1) which is to be sampled. The electronic circuit is further provided with expansion means (EXP) for converting the sampled voltage (UC1) into a sampled output data signal (I0) in a manner such that it corresponds linearly to the input data signal (Ui, Ii). This is achieved, for example, by using a first field effect transistor (T1) for the compression means (CPR) and a second field effect transistor (T2) for the expansion means (EXP). The gate-source voltage of the first field effect transistor (T1) forms the data voltage (U1) which is compressed since the drain-source current of the first field effect transistor (T1) is linear with respect to the input data signal (Ui, Ii). The first (T1) and second (Ti) field effect transistors in fact form a sample and hold current mirror. Thus, though the output current of the sample and hold current mirror is approximately linear with respect to the input current, the output current is a sampled version of the input current.